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Q8. Which type of violation is caused when the signal transition is slower than the library limit?
16 hours ago | [YT] | 0
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Q7. Which physical design metric is represented as the percentage of chip area occupied by cells?
1 day ago | [YT] | 0
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Q6. Which timing path is analyzed from an input port directly to an output port?
2 days ago | [YT] | 1
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Q5. Which physical design optimization reduces excessive net capacitance?
3 days ago | [YT] | 0
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Q4. Which parasitic component becomes dominant in long on-chip interconnects at advanced technology nodes?
4 days ago | [YT] | 0
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Q3. What is the primary objective of cell legalization after placement?
5 days ago | [YT] | 2
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Q2. Which CMOS logic family generally provides the highest noise margin?
6 days ago | [YT] | 0
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Q1. Which design-for-testability (DFT) technique allows internal flip-flops to be controlled and observed during testing?
1 week ago | [YT] | 0
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Answers (21–31)
21. B
22. B
23. A
24. B
25. A
26. B
27. C
28. A
29. A
30. B
31. B
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