21:43
Lab #10 | Digital Logic Design (DLD) – Multiplexer & Demultiplexer | Theory Part
23:42
Lab #9 | Digital Logic Design (DLD)– Encoder & Decoder | Theory Part
11:47
Lab #8 | Digital Logic Design – BCD to 7 Segment Decoder Implementation | Practical Part
18:14
Lab #8 | Digital Logic Design (DLD) – BCD to 7 Segment Decoder | Theory Part
17:04
Lab #7 | Digital Logic Design–4-Bit Binary Parallel Adder–Subtractor Implementation | Practical Part
50:36
Lab #7 | Digital Logic Design – 4-Bit Binary Parallel Adder–Subtractor | Theory Part
16:34
Lab #6 | Digital Logic Design – Half & Full Subtractor Implementation | Practical Part
31:20
Lab #6 | Digital Logic Design – Half Subtractor & Full Subtractor | Theory Part
28:07
Lab #5 | Digital Logic Design – Half Adder & Full Adder | Theory Part
50:51
Lab #4 | Digital Logic Design – Binary to Gray & Gray to Binary Conversion (4-Bit) | Theory Part
13:15
Lab #2 | Digital Logic Design(DLD) - Implementing Logic Gates with NAND & NOR Gates | Practical Part
32:09
Lab #2 | Digital Logic Design - Implementing Logic Expressions Using NAND & NOR Gates | Theory Part
12:28
Lab #1 | Digital Logic Design DLD – Logic Gates AND, NAND & XOR) | Practical Part
36:51
Lab #1 | Digital Logic Design (DLD) – Logic Gates, IC Pins & Truth Table | Theory Part
